The present invention relates to a semiconductor device having a test circuit, and more particularly, to a test circuit of a synchronous DRAM that writes and reads data in synchronism with a clock signal.
To increase the operational speed of SDRAMs, double data rate (DDR)-SDRAMs are now being used instead of single data rate (SDR)-SDRAMs. The rate for reading and writing data in the DDR-SDRAM is twice as great as that of the SDR-SDRAM.
With reference to FIG. 1, when a DDR-SDRAM receives an operation control signal CM (read command), the DDR-SDRAM acquires the read command when a first reference clock signal CLK goes high. When a predetermined read latency RL elapses, the DDR-SDRAM generates a second reference clock signal DQS and output data DQ.
In this state, the output data DQ is output in synchronism with the leading edge and trailing edge of the second reference clock signal DQS. Thus, the data rate of the DDR-SDRAM is twice as great as that of the SDR-SDRAM.
The DDR-SDRAM receives the second reference clock signal DQS and input data DQ during a write mode. The DDR-SDRAM performs data writing in synchronism with the leading edge and trailing edge of the second reference clock signal DQS.
When testing the DDR-SDRAM, the data rate of the DDR-SDRAM may be higher than that of a conventional tester. Thus, to match the data rate of the DDR-SDRAM with that of a tester, the DDR-SDRAM is provided with a test circuit.
With reference to FIG. 2, a typical test circuit 100 includes a test mode switching circuit 3. Data DaN is read in parallel with data DbN from a memory circuit 1. The data DaN, DbN is provided to the multiplexer circuit 2 in accordance with the reference clock signal CLK and the operation control signal CM.
The multiplexer circuit 2 is controlled by the test mode switching circuit 3, which includes switch circuits SW1, SW2. During a normal mode, the second reference clock signal DQS is provided to the multiplexer circuit 2 via the switch circuit SW1. During a test mode, the second reference clock signal DQS and a selection signal SL are provided to the multiplexer circuit 2 via the switch circuits SW1, SW2, respectively. The selection signal SL selects read data DaN or read data DbN.
With reference to FIG. 1, during the normal mode, the multiplexer circuit 2 alternately provides the read data DaN and DbN to the output circuit 4 in synchronism with the leading and trailing edges of the second reference clock signal DQS. The output circuit 4 outputs the read data DaN, DbN as the output data DQ.
Referring to FIG. 3, when the selection signal SL received by the multiplexer circuit 2 goes high during the test mode, the multiplexer circuit 2 provides the read data DaN to the output circuit 4 when the second reference clock signal DQS goes high. The output circuit 4 outputs the read data DaN as the output data DQ.
When the selection signal SL goes low during the test mode, the multiplexer circuit 2 provides the read data DbN to the output circuit 4 when the second reference clock signal DQS goes high. The output circuit 4 outputs the read data DbN as the output data DQ.
In this manner, the test circuit 100 provides the output data DQ to a tester at a data rate that is one half of the data rate of the DDR-SDRAM. The tester compares data prewritten to the memory circuit 1 with the output data DQ and determines whether the DDR-SDRAM is functioning normally.
However, since the data rate of the output data DQ generated by the test circuit 100 is one half of that of the DDR-SDRAM, the time required to read cell information from every memory cell of the memory circuit 1 is twice as long as the time required for the output data DQ to be generated at the normal data rate of the DDR-SDRAM. This prolongs test time and increases test costs.
Further, the test circuit 100 is not capable of detecting whether the DDR-SDRAM is outputting the output data DQ at the normal data rate (i.e., double data rate).
Japanese Unexamined Patent Publication No. 11-101855 describes a test circuit having a frequency divider. The frequency divider divides a reference clock signal, which is provided from an external device, to generate a divisional clock signal. The divisional clock signal is used as the second reference signal to decrease the data rate of the test circuit.
However, when the operational time delay of the frequency divider results in a time lag between the leading edge of the reference clock signal and the leading edge of the divisional clock signal, the tester cannot perform proper comparison of the write data and the read data. To eliminate the time lag between the divisional clock signal and the reference clock signal, a control circuit may be incorporated in the test circuit. However, the control circuit would increase the circuit area of the test circuit. The frequency divider would also increase the circuit area of the test circuit since the frequency divider includes a relatively large number of elements.